COP IEC IEC60191-6-17 Edition 1.0 2011-01 INTERNATIONAL STANDARD NORME INTERNATIONALE Mechanical standardizationof semiconductordevices Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages-Design guide for stacked packages- Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA) Normalisation mecanique desdispositifs a semiconducteurs Partie6-17:Reglesgeneralespourlapreparationdesdessinsd'encombrement des dispositifs a semiconducteurs a montage en surface - Guide de conception pourles boitiers empilés-Boitiers matricielsabilles etapas fins etboitiers matricielsazone de contactplateet apasfins (P-PFBGAet P-PFLGA) material licensed to BR Demo by Thomson Reuters ( THIS PUBLICATION IS COPYRIGHT PROTECTED Copyright@2011IEC,Geneva,Switzerland All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by IEC's member National Committee in the country of the requester. please contact the address below or your local IEC member National Committee for further information. Droits de reproduction reserves. Sauf indication contraire, aucune partie de cette publication ne peut etre reproduite ni utilisée sous quelque forme que ce soit et par aucun procede, électronique ou mecanique, y compris la photocopie et les microfilms, sans I'accord écrit de la CEi ou du Comite national de la CEl du pays du demandeur. Si vous avez des questions sur le copyright de la CEl ou si vous desirez obtenir des droits supplementaires sur cette publication, utilisez les coordonnees ci-apres ou contactez le Comite national de la CEl de votre pays de residence. (Scientific), Inc., IECCentralOffice 3, rue de Varembe CH-1211 Geneva 20 Switzerland Email: inmail@iec.ch Web: www.iec.ch AbouttheIEC International Standards for all electrical, electronic and related technologies. AboutIECpublications The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the latest edition, a corrigenda or an amendment might have been published - Catalogue of IEC publications: www.iec.ch/searchpub The IEc on-line Catalogue enables you to search by a variety of criteria (reference number, text, technical committee...). It also gives information on projects, withdrawn and replaced publications. - IEC Just Published: www.iec.ch/online_news/justpub Stay up to date on all new IEC publications. Just Published details twice a month all new publications released. Available on-line and also by email. - Electropedia: www.electropedia.org The world's leading online dictionary of electronic and electrical terms containing more than 2o ooo terms and definitions in English and French, with equivalent terms in additional languages. Also known as the International Electrotechnical Vocabulary online. • Customer Service Centre: www.iec.ch/webstore/custserv If you wish to give us your feedback on this publication or need further assistance, please visit the Customer Service Centre FAQ or contact us: Email: csc@iec.ch Tel.: +41 22 919 02 11 Fax: +4122 919 03 00 A propos de la CEI La Commission Electrotechnique Internationale (CEl) est la premiere organisation mondiale qui elabore et publie des normes internationales pour tout ce qui a trait a I'électricite, a l'electronique et aux technologies apparentees A propos des publications CEl I'édition la plus recente, un corrigendum ou amendement peut avoir éte publie. : Catalogue des publications de la CEl: www.iec.ch/searchpub/cur_ fut-f.htm reproduction or distribution i Le Catalogue en-ligne de la CEl vous permet d'effectuer des recherches en utilisant differents criteres (numero de reference, texte, comite d'etudes,..). l donne aussi des informations sur les projets et les publications retirees ou remplacees. - Just Published CEl: www.iec.ch/online_news/justpub Restez informe sur les nouvelles publications de la CEl. Just Published detaille deux fois par mo
IEC 60191-6-17 2011 Mechanical standardization of semiconductor devices - Part 6-17 General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guid
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